CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution

The migration of computation to the cloud has raised privacy concerns as sensitive data becomes vulnerable to attacks since they need to be decrypted for processing. Fully Homomorphic Encryption (FHE) mitigates this issue as it enables meaningful computations to be performed directly on encrypted data. Nevertheless, FHE is orders of magnitude slower than unencrypted computation, which hinders its practicality and adoption. Therefore, improving FHE performance is essential for its real world deployment. In this paper, we present a year-long effort to design, implement, fabricate, and post-silicon validate a hardware accelerator for Fully Homomorphic Encryption dubbed CoFHEE. With a design area of $12mm^2$, CoFHEE aims to improve performance of ciphertext multiplications, the most demanding arithmetic FHE operation, by accelerating several primitive operations on polynomials, such as polynomial additions and subtractions, Hadamard product, and Number Theoretic Transform. CoFHEE supports polynomial degrees of up to $n = 2^{14}$ with a maximum coefficient sizes of 128 bits, while it is capable of performing ciphertext multiplications entirely on chip for $n \leq 2^{13}$. CoFHEE is fabricated in 55nm CMOS technology and achieves 250 MHz with our custom-built low-power digital PLL design. In addition, our chip includes two communication interfaces to the host machine: UART and SPI. This manuscript presents all steps and design techniques in the ASIC development process, ranging from RTL design to fabrication and validation. We evaluate our chip with performance and power experiments and compare it against state-of-the-art software implementations and other ASIC designs. Developed RTL files are available in an open-source repository

Towards Integrated Transceivers in mm-Wave Applications

In this paper, we discuss the trend towards higher frequencies in many consumer RF applications. This trend is, on the one hand, a consequence of an apparently endless demand for increased data rates and, on the other hand, being enabled by ongoing developments in IC technology and circuit design. After outlining some of the application trends that are defining the need for integrated transceivers operating in the mm-Wave region, the resulting technology and circuit challenges will be examined

A broadband, inductorless LNA for multi-standard aplications

In this paper a novel broadband, inductor-less, resistive-feedback, CMOS LNA is presented. The amplifier is designed for the frequency band 0.3GHz-2GHz. The measured voltage gain of the implemented LNA is 12dB at 1GHz and the 3dB bandwidth is 2GHz. An IIP3 of-16 dBm and a noise figure of 4dB are measured at 900 MHz. The value of the measured IIP2 is -13dBm. The S11 is better than -10 dB in the frequency band from 300MHz up to 1GHz. The power dissipation is 18mW from a 1.2V supply. The circuit is designed in a digital CMOS 90nm Low Power (LP) process without extra process options

A 1.2 V, inductorless, broadband LNA in 90 nm CMOS LP

This paper presents a novel broadband, induetorless, resistive-feedback CMOS LNA. The LNA is designed for the frequency band 0.4 - 1GHz. The measured power gain of the LNA is 16dB at 1GHz and the 3-dB bandwidth is 2 GHz. A noise figure of 3.5dB and an IIP3 of -17 dBm are measured at 900 MHz. The S11 is better than -10 dB in the frequency band from 300MHz up to 1GHz. The current consumption is 14mA from a 1.2V supply. The circuit is designed in a baseline CMOS 90nm Low Power (LP) process

A 1.2 V, inductorless, broadband LNA in 90 nm CMOS LP

\u3cp\u3eThis paper presents a novel broadband, induetorless, resistive-feedback CMOS LNA. The LNA is designed for the frequency band 0.4 - 1GHz. The measured power gain of the LNA is 16dB at 1GHz and the 3-dB bandwidth is 2 GHz. A noise figure of 3.5dB and an IIP3 of -17 dBm are measured at 900 MHz. The S11 is better than -10 dB in the frequency band from 300MHz up to 1GHz. The current consumption is 14mA from a 1.2V supply. The circuit is designed in a baseline CMOS 90nm Low Power (LP) process.\u3c/p\u3